3.28

SourceProgram/lab5_combination/src/full_adder_tb.v

@@ -5,9 +5,11 @@
 // Engineer:qmj
 ////////////////////////////////////////////////////////////////////////////////
 
-module full_adder_tb_v;
+module full_adder_tb_v(a,b,s,ci,co);
 
 	// Inputs
+	output a,b,ci;
+	input s,co;
 	reg a;
 	reg b;
 	reg ci;

SourceProgram/lab5_combination/src/full_adder_tb.v.bak

+`timescale 1ps / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: zju
+// Engineer:qmj
+////////////////////////////////////////////////////////////////////////////////
+
+module full_adder_tb_v(a,b,s,ci,co);
+
+	// Inputs
+	output a,b,ci;
+	input s,co;
+	reg a;
+	reg b;
+	reg ci;
+
+	// Outputs
+	wire s;
+	wire co;
+
+	// Instantiate the Unit Under Test (UUT)
+	full_adder uut (
+		.a(a), 
+		.b(b), 
+		.s(s), 
+		.ci(ci), 
+		.co(co)
+	);
+
+	initial begin
+  	  a = 0;b = 0;ci = 0;
+	  #100  a = 0;b = 0;ci = 1;
+      #100  a = 0;b = 1;ci = 0;
+	  #100  a = 0;b = 1;ci = 1;
+      #100  a = 1;b = 0;ci = 0;
+	  #100  a = 1;b = 0;ci = 1;
+      #100  a = 1;b = 1;ci = 0;
+	  #100  a = 1;b = 1;ci = 1;
+      #100  $stop;
+	end
+      
+endmodule
+

SourceProgram/lab5_combination/src/mux_2to1_tb.v

@@ -8,6 +8,7 @@
 module mux_2to1_tb_v;
 
 	// Inputs
+
 	reg[3:0] in0;
 	reg[3:0] in1;
 	reg      addr;

SourceProgram/lab5_combination/src/mux_2to1_tb.v.bak

+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: zju
+// Engineer:qmj
+////////////////////////////////////////////////////////////////////////////////
+
+module mux_2to1_tb_v;
+
+	// Inputs
+	reg[3:0] in0;
+	reg[3:0] in1;
+	reg      addr;
+
+	// Outputs
+	wire[3:0] out;
+
+	// Instantiate the Unit Under Test (UUT)
+	mux_2to1 #(.n(4))uut (
+		.out(out), 
+		.in0(in0), 
+		.in1(in1), 
+		.addr(addr)
+	);
+
+	initial begin
+		addr = 0;in0 = 0;in1 = 0;
+		#100  in0 = 5; in1 = 10;	
+        #100  in0 = 6; in1 = 13;
+		#100  addr=1;
+		#100  in0 = 14; in1 = 9;	
+        #100  in0 = 8; in1 = 11;
+		#100 addr=0;
+		#100 $stop;
+		end
+      
+endmodule
+

lab_5/sim/full_adder.cr.mti

+

lab_5/sim/mux_2to1.cr.mti

+E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v
+Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec  3 2014
+-- Compiling module mux_2to1
+
+Top level modules:
+	mux_2to1
+
+} {} {}}