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Commit 5f46d08a authored by Zhuoyu Zhang's avatar Zhuoyu Zhang
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SourceProgram/lab10_StudentID/src/StudentID_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
//
// Create Date: 14:28:15 08/05/2012
// Design Name: stopwatch
// Module Name: E:/lab16_new_201208/ise/stopwatch_tb.v
// Project Name: stopwatch
// Verilog Test Fixture created by ISE for module: stopwatch
////////////////////////////////////////////////////////////////////////////////
module StudentID_tb_v;
parameter DELY=10;
// Inputs
reg clk;
reg reset;
// Outputs
wire a;
wire b;
wire c;
wire d;
wire e;
wire f;
wire g;
wire dp;
wire [3:0] pos;
// Instantiate the Unit Under Test (UUT)
StudentID #(.sim(1'b1)) StudentID_inst(
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.dp(dp),
.pos(pos));
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
#(DELY*2.5+1) reset = 0;
#(DELY*2000) $stop;
end
always #(DELY/2) clk=~clk;
reg[6:0] num;
always @(*)
case({a,b,c,d,e,f,g})
7'b0000001:num=48;//"0" ASCII Code
7'b1001111:num=49;//"1" ASCII Code
7'b0010010:num=50;
7'b0000110:num=51;
7'b1001100:num=52;
7'b0100100:num=53;
7'b0100000:num=54;
7'b0001111:num=55;
7'b0000000:num=56;
7'b0000100:num=57;//"9" ASCII Code
7'b1111111:num=0;
default:num=63; //"?" ASCII Code
endcase
wire[6:0] num0,num1, num2,num3;
assign num0=(pos==4'b1110)? num:7'd0;
assign num1=(pos==4'b1101)? num:7'd0;
assign num2=(pos==4'b1011)? num:7'd0;
assign num3=(pos==4'b0111)? num:7'd0;
endmodule
SourceProgram/lab10_StudentID/src/display_tb .v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module display_tb_v;
parameter DELY=10;
// Inputs
reg clk;
reg scan;
reg [3:0]d0,d1,d2,d3;
// Outputs
wire a;
wire b;
wire c;
wire d;
wire e;
wire f;
wire g;
wire [3:0] pos;
// Instantiate the Unit Under Test (UUT)
display display_inst(
.clk(clk),
.scan(scan),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.pos(pos));
initial begin
// Initialize Inputs
clk = 0;
scan = 0;
#(DELY*2.5+1) d0 =0;d1= 1;d2=2;d3=3;
repeat (12)
begin
#(DELY*3) scan=1;
#DELY scan=0;
end
d0 =4;d1= 5;d2=6;d3=7;
repeat (12)
begin
#(DELY*3) scan=1;
#DELY scan=0;
end
d0 =8;d1= 9;d2=10;d3=11;
repeat (12)
begin
#(DELY*3) scan=1;
#DELY scan=0;
end
#(DELY) $stop;
end
always #(DELY/2) clk=~clk;
reg[6:0] num;
always @(*)
case({a,b,c,d,e,f,g})
7'b0000001:num=48;//"0" ASCII Code
7'b1001111:num=49;//"1" ASCII Code
7'b0010010:num=50;
7'b0000110:num=51;
7'b1001100:num=52;
7'b0100100:num=53;
7'b0100000:num=54;
7'b0001111:num=55;
7'b0000000:num=56;
7'b0000100:num=57;//"9" ASCII Code
7'b1111111:num=0;
default:num=63; //"?" ASCII Code
endcase
wire[6:0] num0,num1, num2,num3;
assign num0=(pos==4'b1110)? num:7'd0;
assign num1=(pos==4'b1101)? num:7'd0;
assign num2=(pos==4'b1011)? num:7'd0;
assign num3=(pos==4'b0111)? num:7'd0;
endmodule
SourceProgram/lab11_button_process_unit/src/button_process_unit_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 10ps
module button_press_tb;
reg clk,ButtonIn,reset;
wire ButtonOut;
parameter delay=10;
//
initial begin
clk = 0; reset = 1; ButtonIn = 0;
#(delay+1) reset=0;
#(delay*100 )
repeat (25)
begin
#(delay*5) ButtonIn=0;
#(delay*5) ButtonIn=1;
end
#(delay*900)
repeat (25)
begin
#(delay*5) ButtonIn=1;
#(delay*5) ButtonIn=0;
end
#(delay*1200)
repeat (25)
begin
#(delay*5) ButtonIn=0;
#(delay*5) ButtonIn=1;
end
#(delay*900)
repeat (25)
begin
#(delay*5) ButtonIn=1;
#(delay*5) ButtonIn=0;
end
#(delay*100)
$stop;
end
//
always #(delay/2) clk=~clk;
//
button_unit #(.sim(1)) button_unit(
.clk(clk),
.reset(reset),
.ButtonIn(ButtonIn),
.ButtonOut(ButtonOut)
);
endmodule
SourceProgram/lab12_stopwatch/src/control_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module control_tb_v;
parameter delay=10;
// Inputs
reg clk;
reg in;
reg reset;
// Outputs
wire clr;
wire count;
// Instantiate the Unit Under Test (UUT)
control control_inst(
.clk(clk),
.reset(reset),
.in(in),
.clr(clr),
.count(count) );
initial
begin
// Initialize Inputs
clk = 0;
in = 0;
reset = 0;
#(delay/2+1) reset = 1;
#(delay) reset = 0;
repeat (5)
begin
#(delay*10) in = 1;
#(delay) in = 0;
end
#(delay*10) $stop;
end
//
always
#(delay/2) clk=~clk;
endmodule
SourceProgram/lab12_stopwatch/src/stopwatch_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module stopwatch_tb;
parameter DELY=10;
// Inputs
reg clk;
reg ButtonIn;
reg reset;
// Outputs
wire a;
wire b;
wire c;
wire d;
wire e;
wire f;
wire g;
wire dp;
wire [3:0] pos;
// Instantiate the Unit Under Test (UUT)
stopwatch #(.sim(1'b1)) uut (
.clk(clk),
.ButtonIn(ButtonIn),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.dp(dp),
.pos(pos),
.reset(reset) );
always #(DELY/2) clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
ButtonIn = 0;
reset = 0;
#(DELY*0.5+1) reset = 1;
#(DELY) reset = 0;
//start
#(DELY*20) ButtonIn = 1;
#(DELY*500) ButtonIn = 0;
#(DELY*15000) ButtonIn = 1;//stop
#(DELY*500) ButtonIn = 0;
#(DELY*1000) ButtonIn = 1;//reset
#(DELY*500) ButtonIn = 0;
#(DELY*100) $stop;
end
reg[6:0] num;
always @(*)
case({a,b,c,d,e,f,g})
7'b0000001:num=48;//"0" ASCII Code
7'b1001111:num=49;//"1" ASCII Code
7'b0010010:num=50;
7'b0000110:num=51;
7'b1001100:num=52;
7'b0100100:num=53;
7'b0100000:num=54;
7'b0001111:num=55;
7'b0000000:num=56;
7'b0000100:num=57;//"9" ASCII Code
default:num=63; //"?" ASCII Code
endcase
wire[6:0] num0,num1, num2,num3;
assign num0=~pos[0]? num:7'd0;
assign num1=~pos[1]? num:7'd0;
assign num2=~pos[2]? num:7'd0;
assign num3=~pos[3]? num:7'd0;
endmodule
SourceProgram/lab12_stopwatch/src/timing_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module timing_tb;
// Inputs
reg clk;
reg en;
reg r;
// Outputs
wire [3:0] q0;
wire [7:0] qs;
wire [3:0] qm;
// Instantiate the Unit Under Test (UUT)
timing uut (
.clk(clk),
.r(r),
.en(en),
.q0(q0),
.qs(qs),
.qm(qm));
//clk
always #50 clk=~clk;
// clr
initial
begin
clk = 0;r=0;en = 0;
#(51) r=1;
#(100)r=0 ;
repeat (620) begin
#(100*3) en=1;
# 100 en=0; end
#1000 $stop;
end
endmodule
SourceProgram/lab15_dds/src/SineROMGenerator.c 0 → 100644
View file @ 5f46d08a
#include<stdio.h>
#include<math.h>
void main()
{
int i ;
int data;
FILE *fp;
if(( fp=fopen("sine_rom.v","w"))==NULL)
{
printf("error");
exit(0);
}
fprintf(fp,"%s\n","module sine_rom( ");
fprintf(fp,"%s\n"," input clk, ");
fprintf(fp,"%s\n"," input wire[9:0] addr, ");
fprintf(fp,"%s\n"," output reg[15:0] dout); ");
fprintf(fp,"%s\n"," always @(posedge clk) ");
fprintf(fp,"%s\n"," case(addr) ");
for(i=0;i<1024;i++)
{
data=(int) (sin(2*3.1415926*i/4096)*32767+0.5);
data &=0x0000ffff;
fprintf(fp,"%s%d%s%d%s\n"," ",i,":dout= 16'd",data,";");
}
fprintf(fp,"%s\n"," endcase ");
fprintf(fp,"%s\n","endmodule");
fclose(fp);
}
SourceProgram/lab15_dds/src/dds_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module dds_tb;
parameter delay=10;
// Inputs
reg clk;
reg reset;
reg [21:0] k;
reg sampling_pulse;
// Outputs
wire new_sample_ready;
wire [15:0] sample;
// Instantiate the Unit Under Test (UUT)
dds dds_inst (
.clk(clk),
.reset(reset),
.k(k),
.sampling_pulse(sampling_pulse),
.new_sample_ready(new_sample_ready),
.sample(sample)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
k ={12'd58, 10'd360};
sampling_pulse= 0;
//
#(delay*1.5+1) reset=0;
repeat (100)
begin
#(delay*5) sampling_pulse= 1;
#(delay) sampling_pulse= 0;
end
//
#(delay) k ={12'd98, 10'd68} ;
repeat (108)
begin
#(delay*5) sampling_pulse= 1;
#(delay) sampling_pulse= 0;
end
#(delay) k ={12'd30, 10'd68} ;
repeat (250)
begin
#(delay*5) sampling_pulse= 1;
#(delay) sampling_pulse= 0;
end
#(delay*5) $stop;
end
//clock
always #(delay/2) clk=~clk;
endmodule
SourceProgram/lab18_AudioLoopBack/src/CodecSetData_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:zju
// Engineer: qmj
////////////////////////////////////////////////////////////////////////////////
module CodecSetData_tb;
// Inputs
reg clk;
reg reset;
reg NewCom;
// Outputs
wire [7:0] SubAddrL;
wire [7:0] data;
wire write;
// Instantiate the Unit Under Test (UUT)
CodecSetData uut (
.clk(clk),
.reset(reset),
.NewCom(NewCom),
.SubAddrL(SubAddrL),
.data(data),
.write(write)
);
initial begin clk = 0;forever #50 clk=~clk;end
initial begin
// Initialize Inputs
reset = 0;
NewCom = 0;
// Wait 100 ns for global reset to finish
#150 reset = 1;
#100 reset = 0;
repeat (30)
begin
#800 NewCom=1;
#100 NewCom=0;
end
#500 $stop;
end
// Add stimulus here
endmodule
SourceProgram/lab18_AudioLoopBack/src/I2cInterface_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module I2cInterface_tb_v;
// Inputs
reg clk;
reg [7:0] SubAddrL;
reg [7:0] data;
reg write;
reg reset;
// Outputs
wire ready;
wire error;
// Bidirs
wire SCL;
wire SDA;
reg link_sda;
// Instantiate the Unit Under Test (UUT)
I2cInterface uut (
.clk(clk),
.SubAddrL(SubAddrL),
.data(data),
.write(write),
.reset(reset),
.ready(ready),
.error(error),
.SCL(SCL),
.SDA(SDA)
);
initial begin clk = 0; forever #50 clk=~clk; end
initial begin
// Initialize Inputs
SubAddrL = 8'h1b;
data = 8'h5a;
write = 0;
reset = 0;
link_sda=0;
// Wait 100 ns for global reset to finish
#100 reset=1;
#100 reset=0;
#150 write=1;
#100 write=0;
#1900 link_sda=1;
#200 link_sda=0;
#1600 link_sda=1;
#200 link_sda=0;
#1600 link_sda=1;
#200 link_sda=0;
#1600 link_sda=1;
#200 link_sda=0;
#2000 $stop;
// Add stimulus here
end
assign SDA=link_sda?1'b0:1'bz;
endmodule
SourceProgram/lab18_AudioLoopBack/src/I2sInterface_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
////////////////////////////////////////////////////////////////////////////////
module IIS_tb;
// Inputs
reg clk;
reg reset;
reg ADC_SDATA;
reg [23:0] LeftPlayData;
reg [23:0] RightPlayData;
// Outputs
wire BCLK;
wire LRCLK;
wire DAC_SDATA;
wire [23:0] LeftRecData;
wire [23:0] RightRecData;
wire NewFrame;
wire MCLK;
// Instantiate the Unit Under Test (UUT)
I2sInterFace uut (
.clk(clk),
.reset(reset),
.BCLK(BCLK),
.LRCLK(LRCLK),
.MCLK(MCLK),
.ADC_SDATA(ADC_SDATA),
.DAC_SDATA(DAC_SDATA),
.LeftPlayData(LeftPlayData),
.RightPlayData(RightPlayData),
.LeftRecData(LeftRecData),
.RightRecData(RightRecData),
.NewFrame(NewFrame)
);
initial begin clk = 0;forever #50 clk=~clk; end
initial begin
// Initialize Inputs
reset = 0;
ADC_SDATA = 0;
LeftPlayData = 0;
RightPlayData = 0;
// Wait 100 ns for global reset to finish
#100 reset = 1;
#100 reset = 0;
LeftPlayData = 24'ha5_a5a5;
RightPlayData =24'h5a_5a5a;
#(100*2200) $stop;
// Add stimulus here
end
always @(*)
ADC_SDATA=DAC_SDATA;
endmodule
SourceProgram/lab19_MusicPlayer/src/AudioInterface.edf 0 → 100644
View file @ 5f46d08a
This source diff could not be displayed because it is too large. You can view the blob instead.
SourceProgram/lab19_MusicPlayer/src/AudioInterface.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
//:
//
//////////////////////////////////////////////////////////////////////////////////
module AudioInterface(
input clk,
input reset,
input ADC_SDATA,
output DAC_SDATA,
output BCLK,
output MCLK,
output LRCLK,
inout SCL,
inout SDA,
output error,
input[23:0] LeftPlayData,
input[23:0] RightPlayData,
output [23:0] LeftRecData,
output [23:0] RightRecData,
output NewFrame
);
endmodule
SourceProgram/lab19_MusicPlayer/src/MusicPlayer.xdc 0 → 100644
View file @ 5f46d08a
create_clock -period 10.000 -name clk -waveform {0.000 5.000} -add
set_property IOSTANDARD LVCMOS33 [get_ports BCLK]
set_property IOSTANDARD LVCMOS33 [get_ports DAC_SDATA]
set_property PACKAGE_PIN U5 [get_ports LRCLK]
set_property IOSTANDARD LVCMOS33 [get_ports LRCLK]
set_property PACKAGE_PIN U6 [get_ports MCLK]
set_property IOSTANDARD LVCMOS33 [get_ports MCLK]
set_property PACKAGE_PIN W5 [get_ports SCL]
set_property IOSTANDARD LVCMOS33 [get_ports SCL]
set_property PACKAGE_PIN V5 [get_ports SDA]
set_property IOSTANDARD LVCMOS33 [get_ports SDA]
set_property PACKAGE_PIN T4 [get_ports ADC_SDATA]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_SDATA]
set_property PACKAGE_PIN R4 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN T5 [get_ports BCLK]
set_property PACKAGE_PIN W6 [get_ports DAC_SDATA]
set_property PACKAGE_PIN D22 [get_ports next_button]
set_property IOSTANDARD LVCMOS33 [get_ports next_button]
set_property PACKAGE_PIN D14 [get_ports play_button]
set_property PACKAGE_PIN T14 [get_ports play]
set_property PACKAGE_PIN U16 [get_ports {song[1]}]
set_property PACKAGE_PIN T16 [get_ports {song[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {song[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {song[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports play]
set_property IOSTANDARD LVCMOS33 [get_ports play_button]
set_property PACKAGE_PIN B22 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
SourceProgram/lab19_MusicPlayer/src/MusicPlayerTop.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer: qmj
//////////////////////////////////////////////////////////////////////////////////
module MusicPLayerTop(
// Clock
input clk,//100MHz
input reset,//高电平有效
// Push button
input play_button, //高电平有效
input next_button, //高电平有效
//Codec Interface
input ADC_SDATA,
output DAC_SDATA,
output BCLK,
output MCLK,
output LRCLK,
inout SCL,
inout SDA,
//3 LED outputs
output[1:0] song,
output play
);
wire sys_clk,audio_clk;
DCM_Audio DCM_inst
(
// Clock out ports
.clk_out1(sys_clk), // output clk_out1
.clk_out2(audio_clk), // output clk_out2
// Status and control signals
.reset(0), // input reset
.locked(), // output locked
// Clock in ports
.clk_in1(clk)); // input clk_in1
// ******************************************************************************
// Button processor units
// ******************************************************************************
wire next;
button_process_unit next_button_process_unit(
.clk(sys_clk),
.reset(reset),
. ButtonIn(next_button),
. ButtonOut(next)); //高电平脉冲
wire play_pause;
button_process_unit play_button_process_unit(
.clk(sys_clk),
.reset(reset),
. ButtonIn(play_button),
. ButtonOut(play_pause)); //高电平脉冲
// ******************************************************************************
// The music player Sample Generate
// ******************************************************************************
wire [15:0] sample;
wire NewFrame;//
music_player music_player_inst(
.clk(sys_clk),
.reset(reset),
.play_pause( play_pause),
.next(next),//(next),
.NewFrame(NewFrame),
.sample(sample),
.play(play),
.song(song));
// ******************************************************************************
// Codec interface
// ******************************************************************************
AudioInterface AudioInterface_inst(
.clk(audio_clk),
.reset(reset),
.BCLK(BCLK),
.LRCLK(LRCLK),
.MCLK(MCLK),
.ADC_SDATA(ADC_SDATA),
.DAC_SDATA(DAC_SDATA),
.LeftPlayData({sample,8'd0}),
.RightPlayData({sample,8'd0}),
.LeftRecData(),
.RightRecData(),
.NewFrame(NewFrame),
.SCL(SCL),
.SDA(SDA),
.error() );
endmodule
SourceProgram/lab19_MusicPlayer/src/button_process_unit.edf 0 → 100644
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SourceProgram/lab19_MusicPlayer/src/button_process_unit.v 0 → 100644
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//
// This module synchronizes, debounces, and one-pulses a button input.
//
module button_process_unit(
input clk,
input reset,
input ButtonIn,
output ButtonOut
);
endmodule
\ No newline at end of file
SourceProgram/lab19_MusicPlayer/src/frequency_rom.v 0 → 100644
View file @ 5f46d08a
module frequency_rom (
clk ,
dout ,
addr
);
input clk;
output [19:0] dout;
input [5:0] addr;
wire [19:0] memory [63:0];
reg [19:0] dout;
always @(posedge clk)
dout = memory[addr];
assign memory[ 0 ] = {10'd0, 10'd0} ; // Note: rest
assign memory[ 1 ] = {10'd9, 10'd395} ; // Note: 1A
assign memory[ 2 ] = {10'd9, 10'd963} ; // Note: 1A#Bb
assign memory[ 3 ] = {10'd10, 10'd573} ; // Note: 1B
assign memory[ 4 ] = {10'd11, 10'd182} ; // Note: 1C
assign memory[ 5 ] = {10'd11, 10'd838} ; // Note: 1C#Db
assign memory[ 6 ] = {10'd12, 10'd557} ; // Note: 1D
assign memory[ 7 ] = {10'd13, 10'd275} ; // Note: 1D#Eb
assign memory[ 8 ] = {10'd14, 10'd81} ; // Note: 1E
assign memory[ 9 ] = {10'd14, 10'd912} ; // Note: 1F
assign memory[ 10 ] = {10'd15, 10'd805} ; // Note: 1F#Gb
assign memory[ 11 ] = {10'd16, 10'd742} ; // Note: 1G
assign memory[ 12 ] = {10'd17, 10'd723} ; // Note: 1G#Ab
assign memory[ 13 ] = {10'd18, 10'd791} ; // Note: 2A
assign memory[ 14 ] = {10'd19, 10'd903} ; // Note: 2A#Bb
assign memory[ 15 ] = {10'd21, 10'd122} ; // Note: 2B
assign memory[ 16 ] = {10'd22, 10'd365} ; // Note: 2C
assign memory[ 17 ] = {10'd23, 10'd652} ; // Note: 2C#Db
assign memory[ 18 ] = {10'd25, 10'd90} ; // Note: 2D
assign memory[ 19 ] = {10'd26, 10'd551} ; // Note: 2D#Eb
assign memory[ 20 ] = {10'd28, 10'd163} ; // Note: 2E
assign memory[ 21 ] = {10'd29, 10'd800} ; // Note: 2F
assign memory[ 22 ] = {10'd31, 10'd587} ; // Note: 2F#Gb
assign memory[ 23 ] = {10'd33, 10'd461} ; // Note: 2G
assign memory[ 24 ] = {10'd35, 10'd423} ; // Note: 2G#Ab
assign memory[ 25 ] = {10'd37, 10'd559} ; // Note: 3A
assign memory[ 26 ] = {10'd39, 10'd783} ; // Note: 3A#Bb
assign memory[ 27 ] = {10'd42, 10'd245} ; // Note: 3B
assign memory[ 28 ] = {10'd44, 10'd731} ; // Note: 3C
assign memory[ 29 ] = {10'd47, 10'd281} ; // Note: 3C#Db
assign memory[ 30 ] = {10'd50, 10'd180} ; // Note: 3D
assign memory[ 31 ] = {10'd53, 10'd79} ; // Note: 3D#Eb
assign memory[ 32 ] = {10'd56, 10'd327} ; // Note: 3E
assign memory[ 33 ] = {10'd59, 10'd576} ; // Note: 3F
assign memory[ 34 ] = {10'd63, 10'd150} ; // Note: 3F#Gb
assign memory[ 35 ] = {10'd66, 10'd922} ; // Note: 3G
assign memory[ 36 ] = {10'd70, 10'd846} ; // Note: 3G#Ab
assign memory[ 37 ] = {10'd75, 10'd95} ; // Note: 4A
assign memory[ 38 ] = {10'd79, 10'd543} ; // Note: 4A#Bb
assign memory[ 39 ] = {10'd84, 10'd491} ; // Note: 4B
assign memory[ 40 ] = {10'd89, 10'd439} ; // Note: 4C
assign memory[ 41 ] = {10'd94, 10'd562} ; // Note: 4C#Db
assign memory[ 42 ] = {10'd100, 10'd360} ; // Note: 4D
assign memory[ 43 ] = {10'd106, 10'd158} ; // Note: 4D#Eb
assign memory[ 44 ] = {10'd112, 10'd655} ; // Note: 4E
assign memory[ 45 ] = {10'd119, 10'd128} ; // Note: 4F
assign memory[ 46 ] = {10'd126, 10'd300} ; // Note: 4F#Gb
assign memory[ 47 ] = {10'd133, 10'd821} ; // Note: 4G
assign memory[ 48 ] = {10'd141, 10'd669} ; // Note: 4G#Ab
assign memory[ 49 ] = {10'd150, 10'd191} ; // Note: 5A
assign memory[ 50 ] = {10'd159, 10'd62} ; // Note: 5A#Bb
assign memory[ 51 ] = {10'd168, 10'd983} ; // Note: 5B
assign memory[ 52 ] = {10'd178, 10'd879} ; // Note: 5C
assign memory[ 53 ] = {10'd189, 10'd101} ; // Note: 5C#Db
assign memory[ 54 ] = {10'd200, 10'd720} ; // Note: 5D
assign memory[ 55 ] = {10'd212, 10'd316} ; // Note: 5D#Eb
assign memory[ 56 ] = {10'd225, 10'd286} ; // Note: 5E
assign memory[ 57 ] = {10'd238, 10'd256} ; // Note: 5F
assign memory[ 58 ] = {10'd252, 10'd600} ; // Note: 5F#Gb
assign memory[ 59 ] = {10'd267, 10'd619} ; // Note: 5G
assign memory[ 60 ] = {10'd283, 10'd314} ; // Note: 5G#Ab
assign memory[ 61 ] = {10'd300, 10'd382} ; // Note: 6A
assign memory[ 62 ] = {10'd318, 10'd125} ; // Note: 6A#Bb
assign memory[ 63 ] = {10'd337, 10'd942} ; // Note: 6B
endmodule
SourceProgram/lab19_MusicPlayer/src/mcu_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: qmj
// Engineer:zju
////////////////////////////////////////////////////////////////////////////////
module mcu_tb_v;
parameter delay=10;
// Inputs
reg clk;
reg reset;
reg play_pause;
reg next;
reg song_done;
// Outputs
wire play;
wire [1:0] song;
wire reset_play;
// Instantiate the Unit Under Test (UUT)
mcu uut (
.clk(clk),
.reset(reset),
.play_pause(play_pause),
.next(next),
.play(play),
.song(song),
.reset_play(reset_play),
.song_done(song_done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
play_pause = 0;
next = 0;
song_done = 0;
//
#(delay*1.5+1) reset=0;
#(delay) play_pause = 1;
#(delay) play_pause = 0;
#(delay*5) play_pause = 1;
#(delay) play_pause = 0;
#(delay*5) play_pause = 1;
#(delay) play_pause = 0;
#(delay*8) next = 1;
#(delay) next = 0;
#(delay*8) song_done = 1;
#(delay) song_done = 0;
#(delay*2) play_pause = 1;
#(delay) play_pause = 0;
#(delay*5) next = 1;
#(delay) next = 0;
#(delay*8) song_done = 1;
#(delay) song_done = 0;
#(delay*5) next = 1;
#(delay) next = 0;
#(delay*5) next = 1;
#(delay) next = 0;
#(delay*5) $stop;
end
//clock
always #(delay/2) clk=~clk;
endmodule
SourceProgram/lab19_MusicPlayer/src/music_player_tb.v 0 → 100644
View file @ 5f46d08a
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: zju
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module music_player_tb_v;
parameter delay=10;
// Inputs
reg clk;
reg reset;
reg play_pause;
reg next;
reg NewFrame;
// Outputs
wire [15:0] sample;
wire play ;
wire [1:0] song ;
// Instantiate the Unit Under Test (UUT)
music_player #(.sim(1)) uut (
.clk(clk),
.reset(reset),
.play_pause(play_pause),
.next(next),
.NewFrame(NewFrame),
.sample(sample),
.play (play),
.song (song));
initial
begin
// Initialize Inputs
clk = 0;
reset = 1;
play_pause = 0;
next = 0;
NewFrame = 0;
//
#(delay+1) reset=0;
#(delay) play_pause = 1;
#(delay) play_pause = 0;
repeat (20000)
begin
#(delay*5) NewFrame = 1;
#(delay) NewFrame = 0;
end
#(delay*10) $stop;
end
//clock
always #(delay/2) clk=~clk;
endmodule
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