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lab_15/src/full_adder.v

+module full_adder(a, b, s, co);
+    input [21:0] a;
+    input [21:0] b;
+    output reg [21:0] s;
+    output reg co;
+    always @*
+        begin
+            {co, s}=a+b;
+        end
+endmodule // full_adder
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