Commit 14252d70 authored by Zhuoyu Zhang's avatar Zhuoyu Zhang
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parent a9da7ce6
module dffre(d, en, r, clk, q);
parameter n = 1;
input en, r, clk;
input [n-1:0] d;
output reg[n-1:0] q;
always @(posedge clk)
if (r) q = {n{1'b0}};
else if(en) q = d;
else q = q;
endmodule // dffre
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