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Zhuoyu Zhang
DigitalSystemLabs
Commits
14252d70
Commit
14252d70
authored
May 16, 2023
by
Zhuoyu Zhang
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lab_15/src/dffre.v
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14252d70
module
dffre
(
d
,
en
,
r
,
clk
,
q
);
parameter
n
=
1
;
input
en
,
r
,
clk
;
input
[
n
-
1
:
0
]
d
;
output
reg
[
n
-
1
:
0
]
q
;
always
@
(
posedge
clk
)
if
(
r
)
q
=
{
n
{
1'b0
}}
;
else
if
(
en
)
q
=
d
;
else
q
=
q
;
endmodule
// dffre
\ No newline at end of file
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