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Zhuoyu Zhang
DigitalSystemLabs
Commits
53e41c8f
Commit
53e41c8f
authored
Apr 04, 2023
by
Zhuoyu Zhang
Browse files
4.4-t
parent
5f46d08a
Changes
3
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lab_5/full_adder.cr.mti
0 → 100644
View file @
53e41c8f
E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder_tb_v
Top level modules:
full_adder_tb_v
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder
Top level modules:
full_adder
} {} {}}
lab_5/src/full_adder.v
View file @
53e41c8f
...
...
@@ -8,5 +8,5 @@ module full_adder (
xor
(
s
,
s1
,
ci
);
and
(
c1
,
a
,
b
);
and
(
c2
,
s1
,
ci
);
xor
(
co
,
c2
,
c1
);
xor
(
co
a
,
c2
,
c1
);
endmodule
\ No newline at end of file
lab_5/vsim.wlf
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53e41c8f
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