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Commit d2d68f75 authored by Zhuoyu Zhang's avatar Zhuoyu Zhang
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SourceProgram/lab5_combination/src/full_adder_tb.v
View file @ d2d68f75
......@@ -5,11 +5,9 @@
// Engineer:qmj
////////////////////////////////////////////////////////////////////////////////
module full_adder_tb_v(a,b,s,ci,co);
module full_adder_tb_v;
// Inputs
output a,b,ci;
input s,co;
reg a;
reg b;
reg ci;
......
lab_5/full_adder.cr.mti
View file @ d2d68f75
E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder_tb_v
Top level modules:
full_adder_tb_v
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder
Top level modules:
full_adder
} {} {}}
lab_5/sim/ModeComparator.mpf 0 → 100644
View file @ d2d68f75
This diff is collapsed.
lab_5/sim/as1.cr.mti 0 → 100644
View file @ d2d68f75
E:/3210105816/digitalsystemlabs/lab_5/src/comp.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/comp.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module comp
Top level modules:
comp
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module mux_2to1
Top level modules:
mux_2to1
} {} {}} E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/abs_dif_tb.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/abs_dif_tb.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module abs_dif_tb
Top level modules:
abs_dif_tb
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/abs_dif.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/abs_dif.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module abs_dif
Top level modules:
abs_dif
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder
Top level modules:
full_adder
} {} {}}
lab_5/sim/as1.mpf 0 → 100644
View file @ d2d68f75
This diff is collapsed.
lab_5/sim/comp.cr.mti 0 → 100644
View file @ d2d68f75
E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/comp_tb.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/comp_tb.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module comp_tb
Top level modules:
comp_tb
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/comp.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/comp.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module comp
Top level modules:
comp
} {} {}}
lab_5/sim/comp.mpf
View file @ d2d68f75
......@@ -820,7 +820,7 @@ Resolution = ns
UserTimeUnit = default
; Default run length
RunLength = 100
RunLength = 100 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 20000
......@@ -2035,9 +2035,9 @@ Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/comp_tb.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1679984910 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1604499008 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = E:/3210105816/digitalsystemlabs/lab_5/src/comp.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1680588039 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
......
lab_5/sim/full_adder.cr.mti
View file @ d2d68f75
E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder_tb_v
Top level modules:
full_adder_tb_v
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module full_adder
Top level modules:
full_adder
} {} {}}
lab_5/sim/full_adder.mpf
View file @ d2d68f75
......@@ -820,7 +820,7 @@ Resolution = ns
UserTimeUnit = default
; Default run length
RunLength = 500 ns
RunLength = 100 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 20000
......@@ -2034,10 +2034,10 @@ Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1679985497 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1679984910 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_0 = E:/3210105816/digitalsystemlabs/lab_5/src/full_adder.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1680588615 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/full_adder_tb.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1680592035 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
......
lab_5/sim/mux_2to1.cr.mti
View file @ d2d68f75
E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v
E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/mux_2to1_tb.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/mux_2to1_tb.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module mux_2to1_tb_v
Top level modules:
mux_2to1_tb_v
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module mux_2to1
Top level modules:
mux_2to1
} {} {}} E:/3210105816/digitalsystemlabs/lab_5/sim/mux_2to1.v {1 {vlog -work work -vopt -stats=none E:/3210105816/digitalsystemlabs/lab_5/sim/mux_2to1.v
Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014
-- Compiling module mux_2to1
......
lab_5/sim/mux_2to1.mpf
View file @ d2d68f75
......@@ -820,7 +820,7 @@ Resolution = ns
UserTimeUnit = default
; Default run length
RunLength = 500 ns
RunLength = 100 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 20000
......@@ -2035,9 +2035,9 @@ Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = E:/3210105816/digitalsystemlabs/SourceProgram/lab5_combination/src/mux_2to1_tb.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1679984910 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = E:/3210105816/digitalsystemlabs/lab_5/src/mux_2to1.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1679988384 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1680586562 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = E:/3210105816/digitalsystemlabs/lab_5/sim/mux_2to1.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1680586562 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
......
lab_5/sim/mux_2to1.v 0 → 100644
View file @ d2d68f75
module mux_2to1(out, in0, in1, addr);
parameter n = 1;
output[n-1:0] out;
input[n-1:0] in0,in1;
input addr;
assign out = addr ? in1 : in0;
endmodule
\ No newline at end of file
lab_5/sim/vsim.wlf
View file @ d2d68f75
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