5.16-写完song_reader模块

lab_15/src/counter.v

+module counter(clk, r, en, q, co);
+parameter n = 2, counter_bits = 1;
+input clk, r, en;
+output co;//进位输出
+output reg [counter_bits-1:0] q = 0;
+assign co = (q == (n-1)) && en;
+always @(posedge clk) begin
+    if(r) q = 0;
+    else if(en) begin
+            if(q == (n-1)) q = 0; //同步清零
+            else q = q + 1; end
+         else q = q;
+end
+endmodule // counter_n
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lab_15/src/mcu.v

+module mcu (play_pause, next, song_done, reset, clk, play, reset_play, song);
+
+input play_pause, next, song_done, reset, clk;
+output play, reset_play;
+output song[1:0];
+
+wire nextsong;
+mcu_ctrl mc(.clk(clk), .reset(reset), .play_pause(play_pause), .next(next), .play(play), .nextsong(nextsong), .reset_play(reset_play), .song_done(song_done));
+
+counter#(.n(4), .counter_bits(2)) cn(.clk(nextsong), .r(0), .en(1), .q(song), .co());
+
+endmodule
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lab_15/src/mcu_ctrl.v

 module mcu_ctrl(clk, reset, play_pause, next,  play, nextsong, reset_play, song_done);
 input clk,reset,song_done,next,play_pause;
+output reg play, reset_play, nextsong;
+parameter RESET = 0, PAUSE = 1 , NEXT = 2, PLAY = 3;// 状态编码
+reg [1:0] state, nextstate;// 现态和次态
 
+//D寄存器
+always @(posedge clk) begin
+    if(reset) state = RESET;
+    else state = nextstate;
+end
 
+//下一状态和输出电路
+always @(*)begin
+    play = 0; nextsong = 0; reset_play = 0;//默认值设置为0
+    case(state)
+        RESET: begin nextstate = PAUSE; reset_play = 1; end
+        PAUSE: begin 
+            if(play_pause) nextstate = PLAY;  
+            else begin if(next) nextstate = NEXT;
+                    else nextstate = PAUSE; end
+            end
+        NEXT: begin nextstate = PLAY; nextsong = 1; reset_play = 1; end
+        PLAY: begin
+            play = 1;
+            if(play_pause) nextstate = PAUSE;  
+            else begin
+                if(next) nextstate = NEXT;
+                else begin
+                    if(song_done) nextstate = RESET;
+                    else nextstate = PLAY; end
+                end
+            end
+        default: nextstate = RESET;
+    endcase
+end
 
 endmodule
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lab_15/src/over.v

+module over(clk, r, din, dout);
+input clk, r;                 
+input [5:0] din;             
+output reg dout;              
+parameter PAUSE = 0, PLAY = 1; 
+reg state, nextstate;     
+
+always @(posedge clk) begin
+    if(r) begin 
+            dout = 1; 
+            state =  PAUSE; 
+        end
+    else state = nextstate;
+end
+
+always @(posedge clk) begin 
+    dout = 0;
+    case (state) 
+        PAUSE: begin 
+            if(din) nextstate = PLAY;   
+            else nextstate = PAUSE; 
+            end 
+        PLAY: begin 
+            if(din == 0) begin 
+                dout = 1; 
+                nextstate = PAUSE; 
+                end      
+            else nextstate = PLAY;              
+            end     
+        default: nextstate = PAUSE;
+    endcase
+end
+endmodule
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lab_15/src/song_reader.v

+module song_reader(clk, reset, play, song, note_done, song_done, note, duration, new_note);
+
+input clk, reset, note_done;
+input[1:0] song;
+output song_done, new_note;
+output[5:0] note, duration;
+
+wire[5:0] q;
+wire co;
+
+// 地址计数器
+conter#(.n(32), .counter_bits(5)) scn(.clk(clk), .r(reset), .en(note_done), .q(q), .co(co));
+// 控制器
+song_reader_ctrl src(.clk(clk), .reset(reset), .note_done(note_done), .play(play), .new_note(new_note));
+// song_rom
+song_rom sr(.clk(clk), .dout({note, duration}), .addr({song, q}));
+// 结束判断
+over ov(.clk(clk), .r(co), .din(duration), .dout(song_done));
+endmodule
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lab_15/src/song_reader_ctrl.v

+module (clk, reset, note_done, play, new_note);
+
+input clk, reset, note_done, play;
+output new_note;
+parameter RESET = 0, NEW_NOTE = 1, WAIT = 2, NEXT_NOTE = 3;
+reg [1:0] state, nextstate;// 现态和次态
+
+
+// D寄存器
+always @(posedge clk) begin
+    if(reset) state = RESET;
+    else state = nextstate;
+end
+
+// 下一状态和输出电路
+always @(posedge clk) begin
+    note_done = 0; play = 0; new_note = 0;
+    case(state)
+        RESET: begin
+            if(play) nextstate = NEW_NOTE;
+            else nextstate = RESET;
+        end
+        NEW_NOTE: begin
+            new_note = 1;
+            nextstate = WAIT;
+        end
+        WAIT: begin
+            new_note = 0;
+            if(play) begin
+                if(note_done) nextstate = NEXT_NOTE;
+                else nextstate = WAIT;
+            end
+            else nextstate = RESET;
+        end
+        NEXT_NOTE: begin
+            new_note = 0;
+            nextstate = NEW_NOTE;
+        end
+        default: nextstate = RESET;
+    endcase
+end
+
+endmodule
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