### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2086221
date_generated | Tue Apr 4 14:49:52 2023 | os_platform | WIN64
product_version | Vivado v2017.4 (64-bit) | project_id | 8cf5c402dcda4a29bba61964bcbc912f
project_iteration | 1 | random_id | 08ef2f2c74475bb79402df210a8dde54
registration_id | 08ef2f2c74475bb79402df210a8dde54 | route_design | TRUE
target_device | xc7a200t | target_family | artix7
target_package | fbg484 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz | cpu_speed | 3000 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 8.000 GB | total_processors | 1

vivado_usage

gui_handlers
basedialog_ok=8 | basedialog_yes=1 | closeplanner_yes=1 | createconstraintsfilepanel_file_location=3
createconstraintsfilepanel_file_name=1 | filesetpanel_file_set_panel_tree=4 | flownavigatortreepanel_flow_navigator_tree=8 | mainmenumgr_export=1
mainmenumgr_file=2 | mainmenumgr_open_recent_file=1 | mainmenumgr_open_recent_project=1 | mainwinmenumgr_layout=2
mainwinmenumgr_load=1 | pacommandnames_goto_netlist_design=1 | pacommandnames_run_bitgen=1 | pacommandnames_save_design=1
primaryclockspanel_recommended_constraints_table=1 | signaltreepanel_signal_tree_table=25 | srcchooserpanel_add_hdl_and_netlist_files_to_your_project=4 | srcchooserpanel_make_local_copy_of_these_files_into=1
timingconstraintswizard_goto_constraints_summary_page=1

java_command_handlers
addsources=1 | runbitgen=1 | runimplementation=1 | runschematic=1
runsynthesis=1 | savedesign=1 | timingconstraintswizard=1 | viewlayoutcmd=1
viewtasksynthesis=1

other_data
guimode=1

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=4 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
ibuf=8 | lut2=1 | lut4=4 | lut5=2
lut6=5 | obuf=4
pre_unisim_transformation
ibuf=8 | lut2=1 | lut4=4 | lut5=2
lut6=5 | obuf=4

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-ruledecks=default::[not_specified] | -upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=0 | bufgctrl_util_percentage=0.00
bufhce_available=120 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=40 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=20 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=40 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=10 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=10 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=740 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=365 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=730 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=365 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00
primitives
ibuf_functional_category=IO | ibuf_used=8 | lut2_functional_category=LUT | lut2_used=1
lut4_functional_category=LUT | lut4_used=4 | lut5_functional_category=LUT | lut5_used=2
lut6_functional_category=LUT | lut6_used=5 | obuf_functional_category=IO | obuf_used=4
slice_logic
f7_muxes_available=66900 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=33450 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=133800 | lut_as_logic_fixed=0 | lut_as_logic_used=10 | lut_as_logic_util_percentage=<0.01
lut_as_memory_available=46200 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=267600 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=0 | register_as_flip_flop_util_percentage=0.00
register_as_latch_available=267600 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=133800 | slice_luts_fixed=0 | slice_luts_used=10 | slice_luts_util_percentage=<0.01
slice_registers_available=267600 | slice_registers_fixed=0 | slice_registers_used=0 | slice_registers_util_percentage=0.00
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=133800 | lut_as_logic_fixed=0
lut_as_logic_used=10 | lut_as_logic_util_percentage=<0.01 | lut_as_memory_available=46200 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_flip_flop_pairs_available=133800 | lut_flip_flop_pairs_fixed=0 | lut_flip_flop_pairs_used=0 | lut_flip_flop_pairs_util_percentage=0.00
slice_available=33450 | slice_fixed=0 | slice_used=4 | slice_util_percentage=0.01
slicel_fixed=0 | slicel_used=4 | slicem_fixed=0 | slicem_used=0
unique_control_sets_used=0 | using_o5_and_o6_fixed=0 | using_o5_and_o6_used=2 | using_o5_output_only_fixed=2
using_o5_output_only_used=0 | using_o6_output_only_fixed=0 | using_o6_output_only_used=8
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

router
usage
actual_expansions=7434 | bogomips=0 | bram18=0 | bram36=0
bufg=0 | bufr=0 | ctrls=0 | dsp=0
effort=2 | estimated_expansions=75888 | ff=0 | global_clocks=0
high_fanout_nets=0 | iob=12 | lut=10 | movable_instances=24
nets=32 | pins=94 | pll=0 | router_runtime=0.000000
router_timing_driven=1 | threads=2 | timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7a200tfbg484-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=abs_dif | -verilog_define=default::[not_specified]
usage
elapsed=00:00:30s | hls_ip=0 | memory_gain=547.895MB | memory_peak=779.660MB

timing_constraints_wizard
usage
accepted_async_clock_groups=0 | accepted_combinational_paths=0 | accepted_external_delays=0 | accepted_false_paths=0
accepted_forwarded_clocks=0 | accepted_generated_clocks=0 | accepted_input_delays=0 | accepted_log_excl_clock_groups=0
accepted_output_delays=0 | accepted_phy_excl_clock_groups=0 | accepted_primary_clocks=0 | missing_async_clock_groups=0
missing_combinational_paths=0 | missing_external_delays=0 | missing_false_paths=0 | missing_forwarded_clocks=0
missing_generated_clocks=0 | missing_input_delays=0 | missing_log_excl_clock_groups=0 | missing_output_delays=0
missing_phy_excl_clock_groups=0 | missing_primary_clocks=0