module timer(
    clk,
    beat, 
    q,       // 计时长度
    din, 
    dout);   // 计时结束输出
input clk, beat, din;
input [5:0] q;    
output dout;      
reg [5:0] cnt = 0;
assign dout = (cnt==q-1);   // 计时结束
always @(posedge clk) begin
    if(din) cnt = 0;      // reset信号
    else begin if(beat) cnt = cnt+1;  // beat高电平则计时+1
               else cnt = cnt; end
end
endmodule // timer