`timescale 1ns / 1ps

module counter_n_tb;
	reg clk;
	reg en;
    reg r;
	wire co;
    wire [2:0] q;

    counter #(.n(5),.counter_bits(3)) uut (.clk(clk), .r(r),  .en(en), 	.q(q), .co(co));

	//clk
    always #50 clk=~clk;
	
	initial 
	    begin
	        clk = 0;r=0;en = 0;
            #(51) r=1;
  	        #(100)r=0;en=1;
            #(800)
            repeat (10)  begin 
	        #(100*3)  en=1;
	        #100 en=0; end
            #100 $stop;
        end
endmodule
